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1 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com features z z z z z single 12v bias supply z z z z z drives all low cost n-mosfets z z z z z high-gain voltage model pwm control z z z z z 300khz/600khz fixed frequency oscillator z z z z z fast transient response : ` high-speed gm amplifier ` full 0 to 100% duty ratio ` external compensation in the control loop z z z z z internal soft-start z z z z z adaptive non-overlapping gate driver z z z z z over-current fault monitor on mosfet, no current sense resistor required z z z z z rohs compliant and 100% lead (pb)-free 12v synchronous buck pwm dc-dc general description the rt8101/a are dc/dc synchronous buck pwm controllers with embedded driver support up to 12v+12v boot-strapped voltage for high efficiency power driving. the parts are with full functions of voltage regulation, power monitoring and protection into a single small footprint packages sop-8 and sop-8 (exposed pad). the rt8101/a apply a high-gain voltage mode pwm control for simple application design. an internal 0.8v reference allows the output voltage to be precisely regulated to low voltage requirement. the parts are proposed with two type including rt8101 and rt8101a with fixed operating frequency of 300khz and 600khz respectively. based on the features that rt8101/a offered, the parts provide an optimum solution between efficiency, total b.o.m. count, and cost. ordering information applications z graphic card z motherboard, desktop servers z ia equipments z telecomm equipments z high power dc-dc regulators pin configurations (top view) sop-8 sop-8(exposed pad) note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. phase boot ugate lgate gnd vcc comp fb 2 3 4 5 8 7 6 boot ugate gnd lgate phase comp vcc fb gnd 2 3 4 5 6 7 8 package type s : sop-8 sp : sop-8 (exposed pad) rt8101/a 600khz 300khz operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard)
2 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 functional pin description boot (pin 1) bootstrap supply for the upper gate driver. connect the bootstrap capacitor between boot pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. ugate (pin 2) upper gate driver output. connect to gate of the high- side power n-channel mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper mos fet is turned off. gnd (pin 3) signal ground for the ic. lgate (pin 4) lower gate driver output. connect to the gate of the low- side power n-channel mosfet. this pin is monitored by the adaptive shoot-through prote ction circuitry to determine when the lower mosfet is turned off. vcc (pin 5) connect this pin to a well-decoupled 12v bias supply. it is also the positive supply for the lower gate driver, lgate. fb (pin 6) buck converter feedback voltage. this pin is the inverting input of the error amplifier. fb senses the switcher output through an external resistor divider network. comp (pin 7) buck converter external compensation. this pin is used to compensate the control loop of the buck converter. phase (pin 8) connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper mosfe t is tur ned off. exposed pad exposed pad should be soldered to pcb board and connected to gnd. typical application circuit 1 2 v v o u t q1 q2 c in rt8101/a v i n ( + 3 . 3 v / + 5 v / + 1 2 v ) psc boot vcc phase ugate lgate fb gnd 1 5 6 3 2 8 4 c o u t l o u t comp r boot r ugate r c 7
3 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com function block diagram driver logic gnd lgate boot ugate phase oc ph_m soft-start & fault logic oscillator power on reset (por) vcc bias voltage reference 1.5v 5vdd ea uv + - + - + - + pwm + - + + - por inhibit ss sse 5v regulator fb + - 0.8v 0.4v 0.8v comp enable 0.4v 30ua 21.6k
4 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 electrical characteristics (v cc = 12v, t a = 25 c, unless otherwise specified) to be continued absolute maximum ratings (note 1) z supply voltage, v cc -------------------------------------------------------------------------------------- 16v z boot, v boot - v phase ------------------------------------------------------------------------------------ 16v z phase to gnd dc ------------------------------------------------------------------------------------------------------------- ? 5v to 15v < 200ns ------------------------------------------------------------------------------------------------------ ? 10v to 30v z boot to phase ------------------------------------------------------------------------------------------ 15v z boot to gnd dc ------------------------------------------------------------------------------------------------------------- ? 0.3v to v cc +15v < 200ns ------------------------------------------------------------------------------------------------------ ? 0.3v to 42v z ugate ------------------------------------------------------------------------------------------------------- v phase ? 0.3v to v boot + 0.3v z lgate ------------------------------------------------------------------------------------------------------- gnd ? 0.3v to v cc + 0.3v z input, output or i/o voltage ----------------------------------------------------------------------------- gnd ? 0.3v to 7v z power dissipation, p d @ t a = 25 c (note 4) sop-8 -------------------------------------------------------------------------------------------------------- 0.83w sop-8 (exposed pad) ----------------------------------------------------------------------------------- 1.33w z package thermal resistance sop-8, ja -------------------------------------------------------------------------------------------------- 120 c/w sop-8 (exposed pad), ja ------------------------------------------------------------------------------ 75 c/w z junction temperature ------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------- 200v recommended operating conditions (note 3) z supply voltage, v cc -------------------------------------------------------------------------------------- 12v 10% z junction temperature range ---------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max units supply input supply voltage v cc ugate and lgate open 10.8 12 13.2 v supply current i cc v cc = 12v -- 3 -- ma power-on reset por th re sh old v cc rt h 8.8 9.6 10.4 v por h ysteresis v cc hys -- 0.8 1.6 v oscillator free running frequency f osc v cc = 12v, rt8101 250 300 350 khz v c c = 12v, rt8101a 500 600 700 khz
5 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com parameter symbol test conditions min typ max units ramp amplitude v os c v cc = 12v -- 1.5 -- v p-p reference voltage pwm error amplifier reference v ref 0.792 0.8 0.808 v error amplifier open loop dc gain a o -- 88 -- db gain-bandwidth product gbw -- 15 -- mh z slew r ate sr -- 6 -- v/us pwm controller gate drivers (v cc = 1 2v) upper gate source i ugat e v boot ? v p hase = 12v, v boot ? v ugate = 6v -- 300 -- ma upper gate source r ugat e v boot ? v p hase = 12v, v boot ? v ugate = 1v -- 7 1 0 upper gate sink r ugat e v boot ? v pha se = 12v, v ugate ? v phase = 1 v -- 4 8 lower gate source i lgate v cc = 12 v, v lgate = 6v -- 500 -- ma lower gate source r lgate v cc ? v lg ate = 1v -- 4 6 lower gate sink r lgate v lgate = 1v -- 2 4 protection under voltage protection measuring v fb 0.3 0.4 0.5 v over current threshold v oc measuring v phas e ? 210 ? 250 ? 290 mv soft-start interval t ss 2 3.2 4.2 ms note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective 4-layers thermal conductivity test board of jedec 51-7 thermal measurement standard.
6 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 typical operating characteristics efficiency vs. output current 0.75 0.80 0.85 0.90 0.95 1.00 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 output current (a) efficiency (%) v cc = 12v v in = 5v rt8101 rt8101a 100 95 90 85 80 75 reference voltage vs. temperature 0.7917 0.7938 0.7959 0.7980 0.8001 0.8022 0.8043 0.8064 -50 -25 0 25 50 75 100 125 temperature reference voltage (v) ( c) v cc = 12v v in = 5v output voltage vs. output current 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 output current (a) output voltage (v) v in = 12v v in = 5v rt8101a output voltage vs. output current 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 output current (a) output voltage (v) v in = 12v v in = 5v rt8101 frequency vs. temperature 280 285 290 295 300 305 310 315 320 325 -40 -10 20 50 80 110 140 temperature frequency (khz) ( c) rt8101 frequency vs. temperature 520 540 560 580 600 620 640 -40 -10 20 50 80 110 140 temperature frequency (khz) ( c) rt8101a
7 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com dead time (rising) time (50ns/div) ugate lgate phase v cc = 12v v in = 12v i out = 25a (5v/div) dead time (falling) time (25ns/div) ugate lgate phase v cc = 12v v in = 12v i out = 25a (5v/div) power on from v cc time (5ms/div) ugate (20v/div) v out (2v/div) v in (10v/div) v cc (10v/div) power off from v cc time (5ms/div) ugate (20v/div) v out (2v/div) v in (10v/div) v cc (10v/div) power on from v in time (5ms/div) ugate (20v/div) v out (2v/div) v in (10v/div) v cc (10v/div) power on from v in time (5ms/div) ugate (20v/div) v out (2v/div) v in (10v/div) v cc (10v/div)
8 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 transient response (rising) time (5 s/div) v out (100mv/div) i out (10a/ div) ugate (20v/div) rt8101a, v cc = v in = 12v, i out = 0a to 15a, f = 1/20ms, sr = 2.5a/us, l = 2.2uh, c = 2000uf transient response (falling) time (5 s/div) rt8101a, v cc = v in = 12v, i out = 15a to 0a, f = 1/20ms, sr = 2.5a/us, l = 2.2uh, c = 2000uf v out (100mv/div) i out (10a/d iv) ugate (20v/div) transient response (falling) time (5 s/div) rt8101, v cc = v in = 12v, i out = 15a to 0a, f = 1/20ms, sr = 2.5a/us, l = 2.2uh, c = 2000uf v out (100mv/div) i out (10a/d iv) ugate (20v/div) transient response (rising) time (5 s/div) v out (100mv/div) i out (10a/ div) ugate (20v/div) rt8101, v cc = v in = 12v, i out = 0a to 15a, f = 1/20ms, sr = 2.5a/us, l = 2.2uh, c = 2000uf
9 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com application information power on reset the rt8101/a automatically initializes upon applying of input power v cc . the power on reset function (por) continually monitors the input bias supply voltage at the vcc pin. the por trip level is typically 9.6v at vcc rising. vin detection after por the rt8101/a continuously generates a 10khz pulse train with 1 s pulse width to turn on the upper mosfet for detecting the existence of v in . rt8101/a keeps monitoring phase pin voltage during the detection period. as soon as the phase voltage crosses 1.5v two times, v in existence is recognized and the rt8101/a initiates its soft start cycle as described in next section. figure 1 soft start a built-in soft-start is used to prevent surge current from v in to v out during power on. after the existence of v in is detected, soft-start (ss) begins automatically. the feedback voltage (v fb) is clamped by internal linear ramping up ss voltage, causing pwm pulse width increasing slowly and thus inducing little surge current. soft-start completes when ss voltage exceeds internal reference voltage (0.8v), the time duration is about 3.2ms. over current protection the rt8101/a senses the current flowing through lower mosfet for over current protection (ocp) by sensing the phase pin voltage as shown in the functional block diagram. + - v in por_h phase ugate phase_m 1.5v internal counter will count (v phase > 1.5v) two times (rising & falling) to recognize when v in is ready. 1st 2nd phase waveform a 30 a current source flows through the internal resistor 21.6k to phase pin causing 0.65v voltage drop across the resistor. ocp is triggered if the voltage at phase pin (drop of lower mosfet v ds ) is lower than ? 0.25v w hen low side mosfet conducting. accordingly inductor current threshold for ocp is a function of conducting resistance of lower mosfet r ds(on) as : ocset ds(on) 30 a 21.6k-0.4v i r = if mosfet with r ds(on) = 10m is us ed, the ocp threshold current is about 25a. once ocp is triggered, the rt8101/a enters hiccup mode and re-soft starts again. the rt8101/a shuts down after ocp hiccups twice. ocp time (2.5ms/div) ugate (10v/div) i out (10a/div) ocp time (2.5ms/div) ugate (10v/div) i out (10a/div) figure 3. power on then shorted figure 4. shorted then power on
10 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 1) modulator frequency equations the modulator transfer function is the small-signal transfer function of v out /v comp (output voltage over the error amplifier output. this transfer function is dominated by a dc gain, a double pole, and a zero as shown in figure 7. the dc gain of the modulator is the input voltage (v in ) divided by the peak to peak oscillator voltage v osc . the output lc filter introduces a double pole, 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. the resonant frequency of the lc filter is expressed as below: out out lc c l 2 1 f = esr c 2 1 f out esr = the esr zero is contributed by the esr associated with the output capacitance. note that this requires that the output capacitor should have enough esr to satisfy s tability requirements. the esr zero of the output capacitor is ex pressed as follows : 2) compensation frequency equations the compensation network consists of the error amplifier and the impedance networks z c and z f as shown in figure 6. figure 6. compensation loop c2 x r2 x 2 1 f z1 = c2 c1 c2 x c1 x r2 x 2 1 f p1 + = + - fb v ref comp ea z c z f c1 c2 r2 r1 r f v out feedback compensation the rt8101/a is a voltage mode controller. the control loop is a single voltage feedback path including a compensator and modulator as sh own in figur e 5. the modulator consists of the pwm comparator and power stage. the pwm comparator compares error amplifier ea output (comp) with oscillator (osc) sawtooth wave to provide a pulse-width modulated (pwm) with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter l out and c out . the output voltage (v out ) is sensed and fed to the inverting input of the error amplifier. a well-designed compensator regulates the output voltage to the reference voltage v ref with fast transient response and good stability. in order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. the goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0db crossing frequency. it is also recommended to manipulate loop frequency response that its gain crosses over 0db at a slope of ? 20db/dec. figure 5. closed loop - + + - osc v osc z fb z in v in driver driver ref pwm comparator comp ea + - ref ea z fb z in v out fb comp c1 c2 c3 r1 r2 r3 esr phase c out v out l out
11 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com figure 7 shows the dc-dc converter's gain vs. frequency. the compensation gain uses external impedance networks z c and z f to provide a stable, high bandwidth loop. high crossover frequency is desirable for fast transient response, but it often jeopardizes the system stability. in order to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency. in the experience, place the zero at 75% lc filter resonant frequency. crossover frequency should be higher than the esr zero but less than 1/5 of the switching frequency. the second pole is placed at half of the s witching frequency. figure 7. bode plot component selection 1) inductor selection the selection of output inductor is based on the considerations of efficiency, output power and operating frequency. low inductance value has smaller size, but results in low efficiency, large ripple current and high output ripple voltage. generally, an inductor that limits the ripple current ( i l ) between 20% and 50% of the output current is appropriate. figure 8 shows the typical topology of synchronous step-down converter and its related waveforms. + s1 s2 v in i s1 i s2 i out v out + - r l r c c out i c v or + - v oc + - v l + - l i l f r e q u e n c y 1 0 h z 1 0 0 h z 1 . 0 k h z 1 0 k h z 1 0 0 k h z 1 . 0 m h z v d b ( v o ) v d b ( c o m p 2 ) v d b ( l o ) - 4 0 0 4 0 8 0 - 6 0 10 1 00 1k 10k 1 00k 1m 80 40 0 20 60 -20 -40 -60 loop gain compensation gain modulator gain frequency (hz) gain (db) figure 8. the waveforms of synchronous step-down converter according to figure 8 the ripple current of inductor can be calculated as follows : (1) where : v in = maximum input voltage v out = output voltage t = s1 turn on time i l = inductor current ripple f s = switching frequency d = duty cycle r c = equivalent series resistor of output capacitor l in out out in in out l out in i fs v v ) v (v l v v d ; fs d t ; t i l v v ? = = = = ? v l v in - v out - v out i l i l = i out i l i s1 i s2 t s t on t off v g1 v g2
12 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 3) input capacitor the selection of input capacitor is mainly based on its maximum ripple current capability. the buck converter draws pulsewise current from the input capacitor during the on time of s1 as shown in figure 8. the r ms value of ripple current flowing through the input capacitor is described as : (6) the input ca pacitor must be capable of handling this ripple current. sometimes, for higher efficiency the low esr capacitor is necessarily. (a) d) - d(1 i rms i out = figure 9. the related waveforms of output capacitor 2) output capacitor the selection of output capacitor depends on the output ripple voltage requirement. practically, the output ripple voltage is a function of both capacitance value and the equivalent series resistance (esr) r c . figure 9 shows the related waveforms of output capacitor. the ac impedance of output capacitor at operating frequency is quite smaller than the load impedance, so the ripple current ( i l ) of the inductor current flows mainly through output capacitor. the output ripple voltage is described as : where v or is caused by esr and v oc by capacitance. for electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the esr of output capacitor. so equation (4) could be simplified as : v out = i l x r c users could connect capacitors in parallel to get calculated esr. (2) (3) (4) (5) out or oc t2 c out l c t1 o 2 out out l l c s ol v v v 1 v i r i dt c 1v v i ir (1d)t 8c =+ =?+ =??+ ? l dt = dt l v out = v or i l i c di l i l 1/2 0 0 i l x r c v oc t1 t2 v oc i l v in -v out t s i out di l thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8101/a, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = ( 125 c ? 25 c) / (120 c/w) = 0.83w for sop-8 packages p d(max) = ( 125 c ? 25 c) / (75 c/w) = 1.33w for psop-8 packages the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance ja . for rt8101/a packages, figure 10 allows the designer to see the effect of rising ambient temperature on the maximum power allowed.
13 rt8101/a preliminary ds8101/a-01 march 2007 www.richtek.com figure 11. the conne ction s of the critical components in the converter + + load + vcc gnd rt8101/a fb lgate ugate il iq1 v out q2 q1 iq2 5v/12v gnd the power components and the pwm controller should be placed firstly. place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. place the output inductor and output capacitors between the mosfets and the load. also locate the pwm controller near by mosfets. a multi-layer printed circuit board is recommended. figure 11 shows the connections of the critical components in the converter. note that the capacitors c in and c out each of them represents numerous physical capacitors. use a dedicated grounding plane and use vias to ground all critical components to this layer. apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase node, but it is not necessary to oversize this particular island. since the phase node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal routing. the pcb traces between the pwm controller and the gate of mosfet and also the traces connecting source of mosfets should be sized to carry 2a peak currents. pcb layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. consider, as an example, the turn-off transition of the upper mosfet prior to turn-off, the upper mosfet was carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the low side mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selections, layout of the critical components, and use shorter and wider pcb traces help in minimizing the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter using the rt8101/a. the switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. figure 10. derating curves for rt8101/a packages 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 20 40 60 80 100 120 140 ambient temperature (c) power dissipation (w) sop-8 psop-8
14 rt8101/a preliminary www.richtek.com ds8101/a-01 march 2007 outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
15 preliminary rt8101/a ds8101/a-01 march 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 1.900 2.700 0.075 0.106 y 1.900 3.600 0.075 0.142

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